Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I²L Technology
نویسندگان
چکیده
An algorithm for parallel multiplication of two n-bit ternary numbers is presented in this brief contribution. This algorithm uses the technique of column compression and computes the product in ( 2 [log, n1 + 2 ) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same algorithm is also applicable to the multiplication of negative numbers.
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ورودعنوان ژورنال:
- IEEE Trans. Computers
دوره 43 شماره
صفحات -
تاریخ انتشار 1994